1. Field of the Invention
The present invention is related to preventing false data output when reading data stored in a semiconductor memory device, and more particularly, to a data output control circuit for the semiconductor memory device that prevents a false data output based on an address transition detecting signal to improve data processing speed.
2. Background of the Related Art
As shown in FIG. 1, a data output control circuit of a related art memory device includes a main amplifier 1, a multiplex/latch unit 2, a data output buffer, an output operator 3A and a delay unit 4. The main amplifier 1 amplifies data DATA, DATA' received from the memory device in accordance with an address transition detecting signal ATD. As shown in FIGS. 1 and 3B, the data DATA' is DATA. The multiplex/latch unit 2 multiplexes and latches in the output from the main amplifier 1. The data output buffer 3 externally outputs data D, D' latched in the multiplex/latch unit 2 in accordance with a select signal SEL. As shown in FIGS. 2 and 3D, the data D' is equal to D. The output operator 3A amplifies to a predetermined level the output from the data output buffer 3 for interfacing with an external circuit (not shown). The delay unit 4 delays the address transition detecting signal ATD for a preset time and outputs the select signal SEL.
With reference to FIGS. 2 and 3A-3F, the operation of the related art data output control circuit will now be described.
First, a high level address transition detecting signal ATD is applied to operate the main amplifier 1. The data DATA, DATA' from the memory device is amplified to a certain level, and then multiplexed and latched in the multiplex/latch unit 2. The address transition detecting signal ATD turns into the select signal SEL via the delay unit 4. As shown in FIG. 3E, the select signal SEL is applied to the data output buffer 3 to control the output of the data D, D' latched in the multiplex/latch unit 2.
The transition of an address signal causes the address transition detecting signal ATD to assume a low level as shown in FIG. 3A. Accordingly, the main amplifier 1 stops operating, which blocks the input of the data DATA, DATA' and the output of the data OUT, OUT' as shown in FIGS. 3B-3C.
When the select signal SEL is applied to the data output buffer 3 via the delay unit 4, a previous cycle's data stored in the multiplex/latch unit 2 or a random data is output via the data output buffer 3 and the output operator 3A to an external circuit as shown in FIG. 3F, thereby resulting in a false data output.
Thus, the related art data output circuit disadvantageously retards the data processing speed because of the output of undesired false data, and accordingly electric current is wasted.
In addition, although the address transition detecting signal ATD restrains a false data output by controlling the output timing of the select signal SEL applied to the output buffer, the false data can be externally transmitted by the data output control circuit at certain timing points because of the difficulty in controlling the output timing.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.